1. Field of the Invention
The present invention relates to a clock circuit and a controlling method of the same, especially to an all-digital spread spectrum clock generating circuit with EMI reduction effect and a method of controlling the same.
2. Description of the Related Art
Recently, digital devices are quite popular. The communication, the exchange, and the processing of the digital data among the digital devices need a clock signal to synchronically transmit the data so as to process the digital signal or the data attached to the digital signal. For example, the CPU in the computer cooperates with the clock signal to allow each digital circuit in the CPU to properly access and process data or control the hardware. Further, in mobile devices, we also need the clock to trigger the transmission of the digital data. If the data are to be accessed among the digital devices accurately, the clock has to be synchronized. Herein, the synchronization can be achieved by dividing or multiplying the frequency so as to acquire different clocks with different clock frequencies but still be synchronized. Accordingly, the digital data can be processed among various digital circuits.
However, the clock speed is constantly increased when the digital system utilizes the digital clock signal provided by the digital clock circuit. Wherein, the EMI (Electromagnetic Interference) is adversely resulted. Namely, the clock signal provided by the digital clock signal unfavorably causes the EMI. Thus, the digital system has to conquer the EMI generated by the clock signal. Moreover, in the design of electronic system, the EMI reduction has to be taken into account. A Spread-Spectrum Clock Generator (SSCG) is mostly applied to reduce the EMI caused by the clock. There are many kinds of circuit structures of the SSCG in the market. A conventional analog spread-spectrum clock generator (Analog SSCG) directly performs a triangular modulation to the controlling voltage of the voltage-controlled oscillator so as to spread the spectrum of the output frequency. This conventional Analog SSCG needs a loop filter with a large on-chip capacitor. Thus, a large chip area has to be occupied by the SSCG circuits. Moreover, in considering the variations that may occur during manufacturing, the variation of capacitance may reach 30%. As a result, the conventional SSCG may be unstable with process variations.
The disclosed digital SSCGs in the market mostly utilize a delta-sigma modulator (DSM) to switch N/N+1, the ratio of the loop divider, so that the output clock frequency can be close to the triangular modulation. However, the phase-locked loop still controls the oscillator according to the frequency error and the phase error compared to the reference clock signal during the triangular modulation. Thus, the phase and frequency tracking of the phase-locked loop to the reference clock signal interferes the triangular modulation. Accordingly, most of the measured modulation of the output frequency is close to a Sine Modulation. Herein, while observing the sine modulation on the power spectrum, peak powers are generated at two sides of the spreading range, which lessens the EMI reduction. Although the Hershey-kiss modulation can solve this problem, the Hershey-kiss modulation is complicated. Consequently, the circuit design of the SSCG with Hershey-kiss modulation also becomes complex. Obviously, the conventional SSCG can not conquer the EMI reduction, and it is also difficult to extensively apply a useful technique to solve the problem. Therefore, we need a technique that can efficiently reduce the EMI while the arrangement of the circuits is simple.
Continuingly, the conventional analog SSCG is disadvantageous in that the design may occupy a large chip area and the power consumption is also high. Limited by the voltage control scheme, the conventional analog SSCG can not be operated in a low voltage system (<1.0V). Thus, it is difficult for the conventional analog SSCG to be designed in the sub-micron manufacturing process with a low supply voltage. Further, the conventional analog SSCG easily affected by the process, voltage, and temperature (PVT) variations, which incurs an abnormal operation.
It brings the present invention to provide an all-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same. The triangular modulation is directly applied to a digital controlled oscillator (DCO) so as to spread a spectrum of an output clock signal. The present invention also utilizes and compares counting results of a reference clock signal and a dividing clock signal to control the output clock signal for maintaining a central frequency of a spread-spectrum clock signal under PVT variations.